MOSFETs with extremely large gate widths, such as power MOSFETs, naturally require more chip area than conventional MOSFETs, and therefore making compact power MOSFETs with large width gates is advantageous, especially when such MOSFETs are part of an integrated circuit, where layout area is a precious commodity. FIG. 1 is a top diagrammatic view of a current type of extended gate MOSFET 20 with large gate width, known as a waffle transistor. The gates 22 are laid out in a crosshatch lattice pattern with sources 24 and drains 26 formed inside the islands formed by the lattice of the gates. The individual sources 24 and drains 26 have silicide overlying regions 28 and are connected together by source contacts 30 to source metal 1 strips 32 and by drain contacts 34 to drain metal 1 strips 36. These metal 1 strips are connected together by metal 2 (not shown) which are also strips and run in a direction to intersect each of the metal 1 strips.
There are several characteristics of the waffle transistor 20 shown in FIG. 1 that limit the operating characteristics of the transistor. The poly sections 38 where the gates cross are about 10% of the total gate poly and do not contribute greatly to the device drive current because they lack access to the source and drain regions. Therefore, the layout area consumed by locations 38 is mostly wasted space. Furthermore, because of the stripped nature of the metallization about ½ of the deposited metal is removed because the minimum metal 1 line and space dimensions are about equal. Also since the metal strips are angled at an optimal 45° with respect to the direction of current flow (the metal 1 and metal 2 intersect each other), the length of the metal is increased by a factor of 1.4 which increases the effective Ron of the transistor. Moreover, the vias between metal 1 and metal 2 can only be made at the intersection of the metal 1 and metal 2, and hence the amount of current which can pass between the two metal layers may be limited by the current capacity of the vias.
Power transistors usually require well taps to improve latchup and safe operating area (SOA) characteristics, which are connections between the sources and the wells with highly doped regions of the same polarity of impurities as the wells which extend from the wells to the source silicides, to provide increased immunity to latch-up of the transistor. However, in the waffle transistor 20 the gates 22 break the sources into small isolated regions, and there is not room to create a butted or integrated well tie in each source 24 of the waffle transistor 20. As a result each source location can be used as a true source or as a well tap. Replacing selected source locations with well ties 40, as shown in FIG. 2, results in a waffle transistor 42 which has lower drive and higher resistance, effectively making the transistor smaller. Moreover, there is a necessary gap between each source and a well tap, which diminishes the effectiveness of the well taps.
It is sometimes advantageous in power transistor arrays to put ballast resistors between the gate and the emitter to protect against electrostatic discharge (ESD) and to balance the current load for each part of or section of the transistor. A common method to form a ballast resistor is to leave a gap between the gate edge and the drain silicide. FIG. 3 shows such ballast resistor gaps 44 in the drain regions of a waffle transistor 46. The reduced area of the drain silicide means that the drain rectangular area must be increased in order to provide the same current density through each drain as shown by the dashed rectangle 48 which corresponds to the perimeter of the one of the drains 26 shown in FIG. 1. As a result the size of each source also grows because the checkerboard grid pattern forces the drain and source squares to be the same size.